(1) Field of the Invention
The present invention relates to a system LSI and a cross-bus apparatus in which two or more pairs of a source apparatus and a destination apparatus, respectively arbitrarily selected from a plurality of apparatuses, are connected simultaneously.
(2) Description of the Prior Art
Recently, what is called large system integration (LSI) has become commercially practical. In the system LSI integration, almost all main parts of a system which would have conventionally been achieved as a plurality of LSIs interconnected on a printed board are integrated into a system LSI.
A merit of the system LSI integration is a low cost achieved by its small size. Another merit among others is reduced delays in signal transfer. There are two types of delays in signal transfer: (1) a delay caused in operation of switching transistors; and (2) a delay caused during signal transfer through wires. Of these, the delay in switching transistors is reduced as the rule for the processing technique becomes minute and the transistor size becomes small. On the contrary, the delay in signal transfer through wires is not much reduced even if the rule for the processing technique becomes minute. This is because the ratio of the delay in signal transfer through wires to the whole signal transfer delay becomes large as the rule for the processing technique becomes minute. For example, the delay in signal transfer through wires to the whole signal transfer delay as a percentage is approximately 50% for LSIs manufactured with the 0.25 μm-rule processing technique, and 80% for LSIs manufactured with the 0.18 μm-rule processing technique. As understood from this, to reduce the whole signal transfer delay, it is indispensable to reduce the delay in signal transfer through wires. To achieve this, it is necessary to design a circuit pattern effectively without impairing the function of the circuit.
Now, the system LSI integration will be described in detail taking a digital broadcast receiver (hereinafter, referred to as DBR) as an example.
FIG. 1 shows a DBR not system-LSI-integrated.
As shown in FIG. 1, a plurality of LSIs (a microcomputer, a transport decoder, an AV decoder, Modem, Glue-ASIC, a DRAM, and a ROM) are interconnected via address buses and data buses disposed on a printed board, where each LSI is further connected to a device or the like.
FIG. 2 shows the construction of a system-LSI-integrated DBR.
As shown in FIG. 2, the system-LSI-integrated DBR includes a DBR system LSI into which almost all of the LSIs shown in FIG. 1 interconnected by buses are integrated. The system-LSI-integrated DBR also includes memories (ROM/FLASH and SDRAM) and other devices.
FIG. 3 shows the construction of the DBR system LSI. The drawing also shows external devices or the like (two “SDRAM”s, a “ROM”, “Other devices”) connected to the DBR system LSI via ports. Note that in the present document, components of the DBR system LSI are called units.
As shown in FIG. 3, a main memory bus 908 is connected to an SDRAM I/F unit 905, an external device I/F unit 906, and a peripheral I/O bus 907 (hereinafter, apparatuses which receive data transfer requests and are connected to a main memory bus, such as the units 905, 906, and 907 connected to the main memory. bus 908, are called “destination apparatuses”). A bus switch unit 920 is connected to: an instruction cache bus 901 connected to an instruction cache in a microcomputer unit 910; a data cache bus 902 connected to a data cache in the microcomputer unit 910; a DMA bus 903 connected to a DMA manager unit 911; a TD bus 904 connected to a transport decoder unit 912 (hereinafter, apparatuses which issue data transfer requests, such as the above units connected to the buses 901 to 904, are called “source apparatuses”); and the main memory bus 908.
FIG. 4 shows a simplified construction of the bus switch unit 920 shown in FIG. 3. The drawing also shows units connected to the bus switch unit 920.
The bus switch unit 920, as shown in FIG. 4, can select one of the instruction cache bus 901, data cache bus 902, DMA bus 903, and TD bus 904 and connect the selected bus to the main memory bus 908.
Here, suppose that two transfer requests for different source apparatuses and different destination apparatuses are issued at the same time, and further suppose that, for example, a request for a transfer from the microcomputer unit 910 to a main memory such as an SDRAM is issued and simultaneously a request for a transfer from a data cache in the microcomputer unit 910 to an I/O device is issued. When this happens, an arbitration unit 921 in the bus switch unit 920 selects one of the transfer requests and turns ON a bus switch corresponding to the selected transfer request so that a master bus and a slave bus corresponding to the selected request are connected while the other not-selected transfer request is kept waiting.
Theoretically, the two transfer requests can be executed simultaneously since the requests specify different source apparatuses and different destination apparatuses. In the above construction, however, one of the simultaneously issued requests is kept waiting. This is because buses on the destination apparatus side are shared.
One technical method for solving this problem is to use cross-bus switches.
FIG. 5 shows the construction of the DBR system LSI using the cross-bus switches. The drawing also shows external devices or the like (two “SDRAM”s, a “ROM”, “Other devices”) connected to the DBR system LSI via ports.
As shown in FIG. 5, a cross-bus switch unit 940 is connected to: the instruction cache bus 901 connected to the instruction cache in the microcomputer unit 910; the data cache bus 902 connected to the data cache in the microcomputer unit 910; the DMA bus 903 connected to the DMA manager unit 911; and the TD bus 904 connected to the transport decoder unit 912 (hereinafter, the buses connected to the source apparatuses are called “source buses”). Also, the cross-bus switch unit 940 is connected to: a high-speed access main memory bus 931 connected to the SDRAM I/F unit 905; a low-speed access main memory bus 932 connected to the external device I/F unit 906; and the peripheral I/O bus 907 (hereinafter, the buses connected to the destination apparatuses are called “destination buses”).
FIG. 6 shows a simplified construction of the cross-bus switch unit 940 shown in FIG. 5. The drawing also shows units connected to the cross-bus switch unit 940.
The cross-bus switch unit 940, as shown in FIG. 6, can select one of the instruction cache bus 901, data cache bus 902, DMA bus 903, and TD bus 904 (hereinafter, such buses on the bus connection requesting side are called “master buses”) for each of the peripheral I/O buses 907, a low-speed access main memory bus 932, and a high-speed access main memory bus 931 (hereinafter, such buses on the bus connection requested side are called “slave buses”) and connect the selected master bus to a corresponding slave bus.
It should be noted here that no bus switches are disposed between the TD bus 904 and the peripheral I/O bus 907, between the TD bus 904 and the low-speed access main memory bus 932, and between the instruction cache bus 901 and the peripheral I/O bus 907. This is because there is a possibility that the transport decoder unit 912 may be connected only to the high-speed access main memory bus 931, and the instruction cache bus 901 of the microcomputer unit 910 is not connected to the peripheral I/O bus 907.
Here, suppose, as in the earlier case of the bus switch unit 920, that a transfer request 1 for transferring from the transport decoder unit 912 to the high-speed access main memory 933 such as an SDRAM is issued and simultaneously a transfer request 2 for transferring from a data cache in the microcomputer unit 910 to the low-speed access main memory 934 such as a hard disk is issued. When this happens, an arbitration unit 941 in the cross-bus switch unit 940 connects the TD bus 904 to the high-speed access main memory bus 931 by turning ON the bus switch 943 corresponding to the transfer request 1; and an arbitration unit 942 in the cross-bus switch unit 940 connects the data cache bus 902 to the low-speed access main memory bus 932 by turning ON the bus switch 944 corresponding to the transfer request 2. As a result, both transfer requests are immediately executed without waiting.
As described above, the DBR system LSI using the cross-bus switch unit differs from the bus switch unit 920 shown in FIG. 4 in that each slave bus of the destination apparatus side can independently perform arbitration. As a result, transfer requests for different source apparatuses and different destination apparatuses are executed without waiting, the transfers being executed simultaneously. Such a system offers a prospect of improvement in the system performance.
However, in such a DBR system LSI using a cross-bus switch unit, most of the buses need to be wired to the cross-bus switch unit. In case of the cross-bus switch unit 940 shown in FIG. 6, seven buses need to be wired: instruction cache bus 901, data cache bus 902, DMA bus 903, TD bus 904, peripheral I/O bus 907, low-speed access main memory bus 932, and high-speed access main memory bus 931. When the number of signal lines per bus is 64, 448 (64×7) signal lines may gather at one place. When such a large number of signal lines gather at one place, the wiring length inevitably becomes large. This decreases wiring efficiency, increases the signal transfer delay remarkably, and causes the operating frequency to level off.